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Preliminary Technical Data
FEATURES
Fast throughput rate: 1.5 MSPS Specified for VDD of 2.7 V to 5.25 V Low power 8 mW max at 1.5 MSPS with 3 V supplies 16 mW max at 1.5 MSPS with 5 V supplies 4 analog input channels with a sequencer Software configurable analog inputs 4-channel single-ended inputs 2-channel fully differential inputs 2-channel pseudo-differential inputs Accurate on-chip 2.5 V reference Wide input bandwidth 70 dB SNR at 50 kHz input frequency No pipeline delays High speed parallel interface--word/byte modes Full shutdown mode: 1 A max 28 lead TSSOP package
4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer AD7933/AD7934
FUNCTIONAL BLOCK DIAGRAM
VDD VREFIN/ VREFOUT VIN0 I/P MUX VIN3 T/H 12-/10-BIT SAR ADC AND CONTROL AGND
AD7933/AD7934
2.5V VREF CLKIN CONVST BUSY
SEQUENCER
PARALLEL INTERFACE/CONTROL REGISTER
VDRIVE
DB0 DB11
CS RD WR W/B
DGND
Figure 1.
GENERAL DESCRIPTION
The AD7933/AD7934 are 12-bit and 10-bit, high speed, low power, successive approximation (SAR) ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates to 1.5 MSPS. The parts contain a low noise, wide bandwidth, differential track-and-hold amplifier that can handle input frequencies up to 20 MHz. The AD7933/AD7934 feature 4 analog input channels with a channel sequencer to allow a consecutive sequence of channels to be converted on. These parts can accept either single-ended, fully differential, or pseudo-differential analog inputs. The conversion process and data acquisition are controlled using standard control inputs, which allows for easy interfacing to microprocessors and DSPs. The input signal is sampled on the falling edge of CONVST and the conversion is also initiated at this point. The AD7933/AD7934 has an accurate on-chip 2.5 V reference that can be used as the reference source for the analog-to-digital conversion. Alternatively, this pin can be overdriven to provide an external reference. These parts use advanced design techniques to achieve very low power dissipation at high throughput rates. They also feature flexible power management options. An on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. High throughput with low power consumption. Four analog inputs with a channel sequencer. Accurate on-chip 2.5 V reference. Software configurable analog inputs. Single-ended, pseudodifferential, or fully differential analog inputs that are software selectable. Single-supply operation with VDRIVE function. The VDRIVE function allows the parallel interface to connect directly to 3 V, or 5 V processor systems independent of VDD. No pipeline delay. Accurate control of the sampling instant via a CONVST input and once off conversion control.
5.
6. 7.
Rev. PrG
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03713-0-001
AD7933/AD7934 TABLE OF CONTENTS
AD7933--Specifications.................................................................. 3 AD7934--Specifications.................................................................. 5 Timing Specifications....................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Terminology .................................................................................... 11 Typical Performance Characteristics ........................................... 13 Control Register.......................................................................... 16 Sequencer Operation ................................................................. 17 Circuit Information ........................................................................ 18 Converter Operation.................................................................. 18 ADC Transfer Function............................................................. 18 Typical Connection Diagram ................................................... 19
Preliminary Technical Data
Analog Input Structure.............................................................. 19 Analog Inputs.............................................................................. 20 Analog Input Selection .............................................................. 22 Reference Section ....................................................................... 22 Parallel Interface......................................................................... 24 Power Modes of Operation....................................................... 27 Power vs. Throughput Rate....................................................... 28 Microprocessor Interfacing....................................................... 28 Application Hints ........................................................................... 30 Grounding and Layout .............................................................. 30 Evaluating the AD7933/AD7934 Performance ...................... 30 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31
REVISION HISTORY
8/04--Revision PrG: Preliminary Version
Rev. PrG | Page 2 of 32
Preliminary Technical Data AD7933--SPECIFICATIONS
AD7933/AD7934
VDD = VDRIVE =2.7 V to 5.25 V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation Aperture Delay2 Aperture Jitter2 Full Power Bandwidth2, 3 DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Total Unadjusted Error Single-Ended and Pseudo Differential Input Offset Error2 Offset Error Match2 Gain Error2 Gain Error Match2 Fully Differential Input Positive Gain Error2 Positive Gain Error Match2 Zero-Code Error2 Zero-Code Error Match2 Negative Gain Error2 Negative Gain Error Match2 ANALOG INPUT Single-Ended Input Range Pseudo-Differential Input Range: VIN+ VIN- Fully Differential Input Range: VIN+ and VIN- VIN+ and VIN- DC Leakage Current5 Input Capacitance REFERENCE INPUT/OUTPUT VREF Input Voltage6 DC Leakage Current5 VREF Input Impedance VREFOUT Output Voltage VREFOUTTemperature Coefficient VREF Noise B Version1 60 60 -73 -73 -75 -75 -75 5 50 20 2.5 10 0.5 0.5 TBD 4.5 0.5 2 0.6 2 0.6 3 1 2 0.6 0 to VREF or 0 to 2 x VREF 0 to VREF or 2 x VREF -0.1 to +0.4 VCM VREF/2 VCM VREF 1 45 10 2.5 1 10 2.5 15 10 130 Unit dB min dB min dB max dB max fa = 40.1 kHz, fb = 51.5 kHz dB typ dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max Twos complement output coding offset LSB max LSB max LSB max LSB max LSB max LSB max V V V V V A max pF typ pF typ V A max k V ppm/C typ V typ V typ
Rev. PrG | Page 3 of 32
Test Conditions/Comments FIN = 50 kHz sine wave
@ 3 dB @ 0.1 dB
Guaranteed no missed codes to 10 bits Straight binary output coding
Depending on RANGE bit setting Depending on RANGE bit setting VCM = common-mode voltage4 = VREF/2 VCM = VREF, VIN+ or VIN- must remain within GND/VDD When in track When in hold 1% specified performance
0.1% @ 25C 0.1 Hz to 10 Hz bandwidth 0.1 Hz to 1 MHz bandwidth
AD7933/AD7934
Parameter VREF Output Impedance VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN5 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD7 Normal Mode(Static) Normal Mode (Operational) Auto StandBy Mode Auto Shutdown Mode Full Shutdown Mode Power Dissipation Normal Mode (Operational) Auto Standby Mode (Static) Auto Shutdown Mode (Static) Full Shutdown Mode B Version1 10 15 25 2.4 0.8 1 10 2.4 0.4 10 10 Unit typ pF typ pF typ V min V max A max pF max V min V max A max pF max Straight (Natural) Binary Twos Complement ns ns max MSPS max V min/max V min/max mA typ mA max mA max mA typ A max mA typ A max A max mW max mW max W max W max W max W max W max W max
Preliminary Technical Data
Test Conditions/Comments When in track When in hold
Typically 10 nA, VIN = 0 V or VDRIVE
ISOURCE = 200 A; ISINK = 200 A
CODING bit = 0 CODING bit = 1
t2 + 13 tclk + t20 135 1.5 2.7/5.25 2.7 /5.25 0.5 3.2 2.6 1.55 90 1 1 1 16 8 450 270 5 3 5 3
Full scale step input
Digital I/Ps = 0 V or VDRIVE VDD = 2.7 V to 5.25 V, SCLK on or off VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V FSAMPLE = 250 kSPS (Static) FSAMPLE = 250 kSPS (Static) SCLK on or off VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V
1 2 3
Temperature range is as follows: B Versions: -40C to +85C. See Terminology section. Analog inputs with slew rates exceeding 27 V/s (full-scale input sine wave >3.5 MHz) within the acquisition time may cause an incorrect conversion result to be returned by the converter. 4 For full common-mode range see 5 Sample tested during initial release to ensure compliance. 6 This device is operational with an external reference in the range 0.1 V to 3.5 V differential mode and 0.1 V to VDD in pseudo-differential and single-ended modes. 7 Measured with a midscale dc input.
Rev. PrG | Page 4 of 32
Preliminary Technical Data AD7934--SPECIFICATIONS
AD7933/AD7934
VDD = VDRIVE = 2.7 V to 5.25 V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation Aperture Delay2 Aperture Jitter2 Full Power Bandwidth2, 3 DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Total Unadjusted Error Single-Ended and Pseudo-Differential Input Offset Error2 Offset Error Match2 Gain Error2 Gain Error Match2 Fully Differential Input Positive Gain Error2 Positive Gain Error Match2 Zero-Code Error2 Zero-Code Error Match2 Negative Gain Error2 Negative Gain Error Match2 ANALOG INPUT Single-Ended Input Range Pseudo-Differential Input Range: VIN+ VIN- Fully Differential Input Range: VIN+ and VIN- VIN+ and VIN- DC Leakage Current5 Input Capacitance REFERENCE INPUT/OUTPUT VREF Input Voltage6 DC Leakage Current VREF Input Impedance VREFOUT Output Voltage VREFOUT Temperature Coefficient VREF Noise B Version1 70 70 -75 -75 -85 -85 -85 5 50 20 2.5 12 1 0.95 TBD 4.5 0.5 2 0.6 2 0.6 3 1 2 0.6 0 to VREF or 0 to 2 x VREF 0 to VREF or 2 x VREF -0.1 to +0.4 VCM VREF/2 VCM VREF 1 45 10 2.5 1 10 2.5 15 10 130 Unit dB min dB min dB max dB max dB typ dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max Twos complement output coding LSB max LSB max LSB max LSB max LSB max LSB max V V V V V A max pF typ pF typ V A max k typ V ppm/C typ V typ V typ
Rev. PrG | Page 5 of 32
Test Conditions/Comments FIN = 50 kHz sine wave
-80 dB typ -82 dB typ fa = 40.1 kHz, fb = 51.5 kHz
@ 3 dB @ 0.1 dB
Guaranteed no missed codes to 12 bits Straight binary output coding
Depending on RANGE bit setting Depending on RANGE bit setting VCM = common-mode voltage4 = VREF/2 VCM = VREF, VIN+ or VIN- must remain within GND/VDD When in track When in hold 1% specified performance
0.1% @ 25C 0.1 Hz to 10 Hz bandwidth 0.1 Hz to 1 MHz bandwidth
AD7933/AD7934
Parameter VREF Output Impedance VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN5 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD7 Normal Mode(Static) Normal Mode (Operational) Auto StandBy Mode Auto Shutdown Mode Full Shutdown Mode Power Dissipation Normal Mode (Operational) Auto Standby Mode (Static) Auto Shutdown Mode (Static) Full Shutdown Mode B Version1 10 15 25 2.4 0.8 1 10 2.4 0.4 10 10 Unit typ pF typ pF typ V min V max A max pF max V min V max A max pF max Straight (Natural) Binary Twos Complement ns ns max MSPS max V min/max V min/max mA typ mA max mA max mA typ A max mA typ A max A max mW max mW max W max W max W max W max W max W max
Preliminary Technical Data
Test Conditions/Comments When in track-and-hold When in track-and-hold
Typically 10 nA, VIN = 0 V or VDRIVE
ISOURCE = 200 A; ISINK = 200 A
CODING bit = 0 CODING bit = 1
t2 + 13 tclk + t20 135 1.5 2.7/5.25 2.7 /5.25 0.5 3.2 2.6 1.55 90 1 1 1 16 8 450 270 5 3 5 3
Full scale step input
Digital I/Ps = 0 V or VDRIVE VDD = 2.7 V to 5.25 V, SCLK on or off VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V FSAMPLE = 250 kSPS (Static) FSAMPLE = 250 kSPS (Static) SCLK on or off VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V
1 2 3
Temperature ranges is as follows: B Versions: -40C to +85C. See Terminology section. Analog inputs with slew rates exceeding 27 V/s (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the converter. 4 For full common mode range see 5 Sample tested during initial release to ensure compliance. 6 This device is operational with an external reference in the range 0.1 V to 3.5 V in differential mode and 0.1 V to VDD in pseudo-differential and single-ended modes. See the Reference Section for more information. 7 Measured with a midscale dc input.
Rev. PrG | Page 6 of 32
Preliminary Technical Data TIMING SPECIFICATIONS1
AD7933/AD7934
VDD = VDRIVE =2.7 V to 5.25 V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 3.
Parameter fCLKIN2 Limit at TMIN, TMAX AD7933 AD7934 10 24 tQUIET t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t133 t144 t15 t16 t17 t18 t19 t20 10 10 20 TBD 0 0 25 10 5 0.5 tCLKIN 0 0 55 50 5 40 15 5 10 0 5 TBD 10 24 10 10 20 TBD 0 0 25 10 5 0.5 tCLKIN 0 0 55 50 5 40 15 5 10 0 5 TBD Unit kHz min MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns max ns min ns min ns min ns min ns min ns min Description
Minimum time between end of read and start of next conversion, i.e., time from when the data bus goes into three-state until the next falling edge of CONVST. CONVST Pulse Width. CONVST Falling Edge to CLKIN Falling Edge Setup Time. CLKIN Falling Edge to BUSY Rising Edge. CS to WR Setup Time. CS to WR Hold Time. WR Pulse Width. Data Setup Time before WR. Data Hold after WR. New Data Valid before Falling Edge of BUSY. CS to RD Setup Time. CS to RD Hold Time. RD Pulse Width. Data Access Time after RD. Bus Relinquish Time after RD. Bus Relinquish Time after RD. HBEN to RD Setup Time. HBEN to RD Hold Time. Minimum Time between Reads/Writes. HBEN to WR Setup Time. HBEN to WR Hold Time. CLKIN Falling Edge to BUSY Rising Edge.
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications given above are with a 25 pF load capacitance. See Figure 37. AD7933/AD7934 Parallel Interface--Conversion and Read Cycle in Word Mode (W/ = 1), Figure 38, Figure 39, and Figure 40. 2 Mark/space ratio for CLKIN is 40/60 to 60/40. 3 The time required for the output to cross TBD. 4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
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AD7933/AD7934 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to AGND/DGND VDRIVE to AGND/DGND Analog Input Voltage to AGND Digital Input Voltage to DGND VDRIVE to VDD Digital Output Voltage to AGND VREFIN to AGND AGND to DGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Reflow Temperature (10 sec to 30 sec) ESD Rating -0.3 V to +7 V -0.3 V to VDD +0.3 V -0.3 V to VDD + 0.3 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to +0.3 V 10 mA -40C to +85C -65C to +150C 150C 97.9C/W (TSSOP) 14C/W (TSSOP) 255C 2 kV
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Transient currents of up to 100 mA will not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrG | Page 8 of 32
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1 W/B DB1 DB2 DB3 DB4 DB5
2 28 27 26
AD7933/AD7934
VIN3 VIN2 VIN1 VIN0 VREFIN/VREFOUT AGND CS RD WR CONVST CLKIN BUSY DB10
03713-0-006
DB0 3
4 5 6 7 8
AD7933/
AD7934 TOP VIEW (Not to Scale)
25 24 23 22 21 20 19 18 17 16 15
DB6 9 DB7 10 VDRIVE 11 DGND 12 DB8/HBEN 13 DB9 14
DB11
Figure 2. Pin Configuration
Table 5. Pin Function Description
Pin No. 1 2 Mnemonic VDD W/B Description Power Supply Input. The VDD range for the AD7933/AD7934 is from 2.7 V to 5.25 V. The supply should be decoupled to AGND with a 0.1 F capacitor and a 10 F tantalum capacitor. Word/Byte Input. When this input is logic high, word transfer mode is enabled and data is transferred to and from the AD7933/AD7934 in 12-/10-bit words on Pins DB0/DB2 to DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID is transferred on Pins DB0 to DB7 and Pin DB8/HBEN assumes its HBEN functionality. Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control register to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. When reading from the AD7933, the two LSBs (DB0 and DB1) are always 0 and the LSB of the conversion result is available on DB2. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7933/AD7934 will operate. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD but should never exceed VDD by more than 0.3 V. Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to or read from the AD7933/AD7934 are on DB0 to DB3 When reading from the device, DB4 of the high byte is always 0 and DB5 and DB6 will contain the ID of the channel for which the conversion result corresponds (see Channel Address Bits in Table 9). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from the AD7933, the two LSBs in the low byte are 0s and the remaining 6 bits, conversion data. Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output will go low. The track-and-hold returns to track mode just prior to the falling edge of BUSY, and the acquisition time for the part begins when BUSY goes low. Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7933/AD7934 takes 13.5 clock cycles. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following power-down, when operating in the auto shutdown or auto standby mode, a rising edge on CONVST is used to power up the device.
Rev. PrG | Page 9 of 32
3 to 10
DB0 to DB7
11
VDRIVE
12
DGND
13
DB8/HBEN
14 to 16
DB9 to DB11
17
BUSY
18
CLKIN
19
CONVST
AD7933/AD7934
Pin No. 20 21 22 23 Mnemonic WR RD CS AGND
Preliminary Technical Data
Description Write Input. Active low logic input used in conjunction with CS to write data to the control register. Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or write data to the control register. Analog Ground. This is the ground reference point for all analog circuitry on the AD7933/AD7934. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by an external reference. The input voltage range for the external reference is 0.1 V to 3.5 V for differential mode and is 0.1 V to VDD in single-ended and pseudo-differential mode, depending on VDD. Analog Input 0 to Analog Input 3. Four analog input channels that are multiplexed into the on-chip track-andhold. The analog inputs can be programmed to be four single ended inputs, two fully differential pairs or two pseudo-differential pairs by setting the MODE bits in the control register appropriately (see Table 9). The analog input channel to be converted can either be selected by writing to the address bits (ADD1 and ADD0) in the control register prior to the conversion, or the on-chip sequencer can be used. The input range for all input channels can either be 0 V to VREF or 0 V to 2 x VREF and the coding can be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register. Any unsed input channels should be connected to AGND to avoid noise pickup.
24
VREFIN/VREFOUT
25 to 28
VIN0 to VIN3
Rev. PrG | Page 10 of 32
AD7933/AD7934 TERMINOLOGY
Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (00 . . .000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB Offset Error Match This is the difference in offset error between any two channels. Gain Error This is the deviation of the last code transition (111 . . .110) to (111 . . . 111) from the ideal (i.e., VREF - 1 LSB) after the offset error has been adjusted out. Gain Error Match This is the difference in gain error between any two channels. Zero-Code Error This applies when using the twos complement output coding option, in particular to the 2 x VREF input range with -VREF to +VREF biased about the VREFIN point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal VIN voltage, i.e., VREF. Zero-Code Error Match This is the difference in zero-code error between any two channels. Positive Gain Error This applies when using the twos complement output coding option, in particular to the 2 x VREF input range with -VREF to +VREF biased about the VREFIN point. It is the deviation of the last code transition (011. . .110) to (011 .. . 111) from the ideal (i.e., +VREF - 1 LSB) after the zero-code error has been adjusted out. Positive Gain Error Match This is the difference in positive gain error between any two channels. Negative Gain Error This applies when using the twos complement output coding option, in particular to the 2 x VREF input range with -VREF to +VREF biased about the VREF point. It is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., -VREFIN + 1 LSB) after the zero-code error has been adjusted out.
Rev. PrG | Page 11 of 32
Preliminary Technical Data
Negative Gain Error Match This is the difference in negative gain error between any two channels. Channel-to-Channel Isolation It is a measure of the level of crosstalk between channels. It is measured by applying a full-scale sine wave signal to the three nonselected input channels and applying a 50 kHz signal to the selected channel. The channel-to-channel isolation is defined as the ratio of the power of the 50 kHz signal on the selected channel to the power of the noise signal that appears in the FFT of this channel. Power Supply Rejection Ratio (PSRR) It is defined as the ratio of the power in the ADC output at fullscale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency fS. The frequency of the input varies from 1 kHz to 1 MHz. PSRR (dB) = 10log(Pf/PfS) Pf is the power at frequency f in the ADC output; PfS is the power at frequency fS in the ADC output. Track-and-Hold Acquisition Time The track-and-hold amplifier returns into track mode and the end of conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion. Signal-to-(Noise + Distortion) Ratio (SINAD) This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB, and for a 10-bit converter, this is 62 dB.
AD7933/AD7934
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7933/AD7934, it is defined as
Preliminary Technical Data
Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb).
THD (dB ) = -20log
V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak
The AD7933/AD7934 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.
Rev. PrG | Page 12 of 32
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, unless otherwise noted.
AD7933/AD7934
Figure 3. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
Figure 6. AD7934 FFT @ VDD = 5 V
Figure 4. Channel-to-Channel Isolation
Figure 7. AD7934 Typical DNL @ VDD = 5 V
Figure 5. AD7934 SINAD vs. Analog Input Frequency for Various Supply Voltages
Figure 8. AD7934 Typical INL @ VDD = 5 V
Rev. PrG | Page 13 of 32
AD7933/AD7934
Preliminary Technical Data
Figure 9. AD7934 Change in INL vs. VREF for VDD = 5 V
Figure 12. AD7934 Offset vs. VREF
Figure 10.AD7934 Change in DNL vs. VREF for VDD = 5 V
Figure 13. AD7934 Histogram of Codes @ VDD = 5 V with the Internal Reference
Figure 11. AD7934 Change in ENOB vs. VREF for VDD = 5 V
Figure 14. AD7934 Histogram of Codes @ VDD = 5 V with an External Reference
Rev. PrG | Page 14 of 32
Preliminary Technical Data
AD7933/AD7934
Figure 15. AD7933 FFT @ VDD = 5 V
Figure 17. AD7933 Typical INL @ VDD = 5 V
Figure 16. AD7933 Typical DNL @ VDD = 5 V
Rev. PrG | Page 15 of 32
AD7933/AD7934
CONTROL REGISTER
Preliminary Technical Data
The control register on the AD7933/AD7934 is a 12-bit, write-only register. Data is written to this register using the CS and WR pins. The control register is shown below and the functions of the bits are described in Table 7. At power-up, the default bit settings in the control register are all 0s.
Table 6. Control Register Bits
MSB D11 PM1 D10 PM0 D9 CODING D8 REF D7 ZERO D6 ADD1 D5 ADD0 D4 MODE1 D3 MODE0 D2 SEQ1 D1 SEQ0 LSB D0 RANGE
Table 7. Control Register Bit Function Description
Bit No. 11, 10 9 8 7 6, 5 4, 3 2 1 0 Mnemonic PM1, PM0 CODING REF ZERO ADD1, ADD0 MODE1, MODE0 SEQ1 SEQ0 RANGE Description Power Management Bits. These two bits are used to select the power mode of operation. The user can choose between either normal mode or various power-down modes of operation as shown in Table 8. This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight (natural) binary. If this bit is set to 1, the output coding is twos complement. This bit selects whether the internal or an external reference is used to perform the conversion. If this bit is Logic 0, an external reference should be applied to the VREF pin, and if it is Logic 1, the internal reference is selected (see the Reference Section). This bit is not used so it should always be set to Logic 0. These two address bits are used to either select which analog input channel is to be converted in the next conversion, if the sequencer is not being used, or to select the final channel in a consecutive sequence when the sequencer is being used as described in Table 10. The selected input channel is decoded as shown in Table 9. The two mode pins select the type of analog input on the four VIN pins. The AD7933/AD7934 have either four single-ended inputs, two fully differential inputs, or two pseudo-differential inputs (see Table 9). The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the sequencer function (see Table 10). The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the sequencer function (see Table 10). This bit selects the analog input range of the AD7933/AD7934. If it is set to 0, the analog input range extends from 0 V to VREF. If it is set to 1, the analog input range extends from 0 V to 2 x VREF. When this range is selected, AVDD must be 4.75 V to 5.25 V.
Table 8. Power Mode Selection using the Power Management Bits in the Control Register
PM1 0 0 1 1 PM0 0 1 0 1 Mode Normal Mode Auto Shutdown Auto Standby Full Shutdown Description When operating in normal mode, all circuitry is fully powered up at all times. When operating in auto shutdown mode, the AD7933/AD7934 will enter full shutdown mode at the end of each conversion. In this mode, all circuitry is powered down. When the AD7933/AD7934 enter this mode, all circuitry is partially powered down. This mode is similar to the auto shutdown mode but it allows the part to power up in 1 s. When the AD7933/AD7934 enters this mode, all circuitry is powered down. The information in the control register is retained.
Rev. PrG | Page 16 of 32
Preliminary Technical Data
Table 9. Analog Input Type Selection
Channel Address MODE0 = 0, MODE1 = 0 Four Single-Ended I/P Channels VIN+ VIN- VIN0 AGND VIN1 AGND VIN2 AGND VIN3 AGND MODE0 = 0, MODE1 = 1 Two Fully Differential I/P Channels VIN+ VIN- VIN0 VIN1 VIN1 VIN0 VIN2 VIN3 VIN3 VIN2 MODE0 = 1, MODE1 = 0 Two Pseudo-Differential I/P Channels VIN+ VIN- VIN0 VIN1 VIN1 VIN0 VIN2 VIN3 VIN3 VIN2
AD7933/AD7934
MODE0 = 1, MODE1 = 1 Not Used
ADD1 0 0 1 1
ADD0 0 1 0 1
SEQUENCER OPERATION
The configuration of the SEQ0 and SEQ1 bits in the control register allow the user to use the sequencer function. Table 10 outlines the two sequencer modes of operation.
Table 10. Sequence Selection Modes
SEQ0 0 0 1 1 SEQ1 0 1 0 1 Sequence Type This configuration is selected when the sequence function is not used. The analog input channel selected on each individual conversion is determined by the contents of the channel address bits, ADD1 and ADD0, in each prior write operation. This mode of operation reflects the normal operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7933/AD7934 selects the next channel for conversion. Not Used. Not Used. This configuration is used in conjunction with the channel address bits, ADD1 and ADD0, to program continuous conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by the channel address bits in the control register. When in differential or pseudo-differential mode, inverse channels (e.g., VIN1, VIN0) are not converted in this mode.
Rev. PrG | Page 17 of 32
AD7933/AD7934 CIRCUIT INFORMATION
The AD7933/AD7934 are fast, 4-channel, 12-bit and10-bit, single-supply, successive approximation analog-to-digital converters. The parts operate from either a 2.7 V to 3.6 V or 4.75 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS. The AD7933/AD7934 provide the user with an on-chip trackand-hold, an internal accurate reference, an analog-to-digital converter, and a parallel interface housed in a 28-lead TSSOP package. The AD7933/AD7934 have four analog input channels that can be configured to be four single-ended inputs, two fully differential pairs, or two pseudo-differential pairs. There is an on-chip channel sequencer that allows the user to select a consecutive sequence of channels through which the ADC can cycle with each falling edge of CONVST. The analog input range for the AD7933/AD7934 is 0 to VREF or 0 to 2 x VREF, depending on the status of the RANGE bit in the control register. The output coding of the ADC can be either binary or twos complement, depending on the status of the CODING bit in the control register. The AD7933/AD7934 provide flexible power management options to allow users to achieve the best power performance for a given throughput rate. These options are selected by programming the power management bits, PM1 and PM0, in the control register.
Preliminary Technical Data
When the ADC starts a conversion (Figure 19), SW3 will open and SW1 and SW2 will move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC's output code. The output impedances of the sources driving the VIN+ and the VIN- pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors.
CAPACITIVE DAC
COMPARATOR VIN+ B A A B CS SW1 SW3 VIN- SW2 VREF CS
CONTROL LOGIC
CAPACITIVE DAC
Figure 19. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7933/AD7934 is either straight binary or twos complement, depending on the status of the CODING bit in the control register. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on) and the LSB size is VREF/1024 for the AD7933 and VREF/4096 for the AD7934. The ideal transfer characteristics of the AD7933/AD7934 for both straight binary and twos complement output coding are shown in Figure 20 and Figure 21, respectively.
CONVERTER OPERATION
The AD7933/AD7934 are a successive approximation ADC based on two capacitive DACs. Figure 18 and Figure 19 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises of control logic, a SAR, and two capacitive DACs. Both figures show the operation of the ADC in differential/pseudo-differential mode. Single-ended mode operation is similar but VIN- is internally tied to AGND. In the acquisition phase, SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.
CAPACITIVE DAC
111...111 111...110
ADC CODE
111...000 011...111 1 LSB = VREF/4096 (AD7934) 1 LSB = VREF/1024 (AD7933)
COMPARATOR VIN+ B A A B CS SW1 SW3 VIN- SW2 VREF CS
000...010 000...001 000...000 0V
CONTROL LOGIC
1 LSB ANALOG INPUT
+VREF-1 LSB
CAPACITIVE DAC
03713-0-023
NOTE: VREF IS EITHER VREF OR 2 x VREF
Figure 18. ADC Acquisition Phase
Figure 20. AD7933/AD7934 Ideal Transfer Characteristic with Straight Binary Output Coding
Rev. PrG | Page 18 of 32
03713-0-025
03713-0-024
Preliminary Technical Data
1 LSB = 2 x VREF/4096 (AD7934) 1 LSB = 2 x VREF/1024 (AD7933) 011...111 011...110
AD7933/AD7934
ANALOG INPUT STRUCTURE
Figure 23 shows the equivalent circuit of the analog input structure of the AD7933/AD7934 in differential/pseudodifferential mode. In single-ended mode, VIN- is internally tied to AGND. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part.
03713-0-026
ADC CODE
000...001 000...000 111...111
100...010 100...001 100...000 -VREF + 1 LSB VREF +VREFV - 1 LSB
Figure 21. AD7933/AD7934 Ideal Transfer Characteristic with Twos Complement Output Coding
TYPICAL CONNECTION DIAGRAM
Figure 22 shows a typical connection diagram for the AD7933/AD7934. The AGND and DGND pins are connected together at the device for good noise suppression. The VREFIN/VREFOUT pin is decoupled to AGND with a 0.47 F capacitor to avoid noise pickup, if the internal reference is used. Alternatively, VREFIN/VREFOUT can be connected to a external reference source, and in this case, the reference pin should be decoupled with a 0.1 F capacitor. In both cases, the analog input range can either be 0 V to VREF (RANGE bit = 0) or 0 V to 2 x VREF (RANGE bit = 1). The analog input configuration is either four single-ended inputs, two differential pairs or two pseudo-differential pairs (see Table 9). The VDD pin connects to either a 3 V or 5 V supply. The voltage applied to the VDRIVE input controls the voltage of the digital interface, and here, it is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section).
0.1F 10F 3V/5V SUPPLY
The C1 capacitors, in Figure 23, are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 . The C2 capacitors, in Figure 23, are the ADC's sampling capacitors and have a typical capacitance of 16 pF. For ac applications, removing high frequency components from the analog input signal is recommended by using an RC lowpass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.
VDD D VIN+ C1 D
R1
C2
VDD D
W/B VIN0 0 TO VREF/ 0 TO 2 x VREF CLKIN CS VIN3 RD WR BUSY CONVST AGND DGND VREFIN/VREFOUT 2.5V VREF DB0 DB11/DB9 VDRIVE 0.1F 10F 3V SUPPLY 0.1F EXTERNAL VREF 0.47F INTERNAL VREF C/P
Figure 23. Equivalent Analog Input Circuit, Conversion Phase--Switches, Open Track Phase--Switches Closed
Figure 22. Typical Connection Diagram
Rev. PrG | Page 19 of 32
03713-0-027
When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 24 shows a graph of the THD versus the analog input signal frequency for different source impedances for both VDD = 5 V and 3 V.
03713-0-028
VDD
AD7933/AD7934
VIN- C1 D
R1
C2
AD7933/AD7934
+1.25V 0V -1.25V VIN R 3R
Preliminary Technical Data
R +2.5V 0V VIN0 VIN3 VREFOUT
AD7933/ AD7934*
0.47F
03713-0-031
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. Single-Ended Mode Connection Diagram Figure 24. THD vs. Analog Input Frequency for Various Source Impedances
Differential Mode
The AD7933/AD7934 can have two differential analog input pairs by setting Bits MODE0 and MODE1 in the control register to 0 and 1, respectively. Differential signals have some benefits over single-ended signals, including noise immunity based on the device's common-mode rejection and improvements in distortion performance. Figure 27 defines the fully differential analog input of the AD7933/AD7934.
VREF p-p
Figure 25 shows a graph of the THD versus the analog input frequency for various supplies, while sampling at 1.5 MHz with an SCLK of 20 MHz. In this case, the source impedance is 10 .
VIN+
AD7933/ AD7934*
VIN-
03713-0-032
COMMON-MODE VOLTAGE
VREF p-p
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. THD vs. Analog Input Frequency for Various Supply Voltages Figure 27. Differential Input Definition
ANALOG INPUTS
The AD7933/AD7934 have software selectable analog input configurations. Users can choose either four single-ended inputs, two fully differential pairs, or two pseudo-differential pairs. The analog input configuration is chosen with Bits MODE0/MODE1 in the internal control register (see Table 9).
Single-Ended Mode
The AD7933/AD7934 can have four single-ended analog input channels by setting the MODE0 and MODE1 bits in the control register both to 0. In applications where the signal source has a high impedance, it is recommended to buffer the analog input before applying it to the ADC. The analog input range is either 0 to VREF or 0 to 2 x VREF. If the analog input signal to be sampled is bipolar, the internal reference of the ADC can be used to externally bias up this signal to make it of the correct format for the ADC. Figure 26 shows a typical connection diagram when operating the ADC in single-ended mode.
The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN- pins in each differential pair (i.e., VIN+ - VIN-). VIN+ and VIN- should be simultaneously driven by two signals, each of amplitude VREF that are 180 out of phase. The amplitude of the differential signal is therefore -VREF to +VREF peak-to-peak (i.e., 2 x VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, i.e. (VIN+ + VIN-)/2, and is therefore the voltage that the two inputs are centered on. This results in the span of each input being CM VREF/2. This voltage has to be set up externally and its range varies with VREF. As the value of VREF increases, the common-mode range decreases. When driving the inputs with an amplifier, the actual common-mode range is determined by the amplifier's output voltage swing. Figure 28 and Figure 29 show how the common-mode range typically varies with VREF for both a 5 V and a 3 V power supply. The common mode must be in this range to guarantee the functionality of the AD7933/AD7934.
Rev. PrG | Page 20 of 32
Preliminary Technical Data
When a conversion takes place, the common mode is rejected resulting in a virtually noise free signal of amplitude -VREF to +VREF corresponding to the digital codes of 0 to 1024 for the AD7933 and 0 to 4096 for the AD7934.
3.5 3.0
AD7933/AD7934
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7933/AD7934. The circuit configurations shown in Figure 30 and Figure 31 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. A suitable dual op amp that could be used in this configuration to provide differential drive to the AD7933/AD7934 is the AD8022. Take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. The driver circuits in Figure 30 and Figure 31 are optimized for dc coupling applications requiring best distortion performance. The circuit configuration shown in Figure 30 converts a unipolar, single-ended signal into a differential signal. The circuit configuration in Figure 31 is configured to convert and level shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the VREF level of the ADC.
220 2 x VREF p-p VREF GND 390
03713-0-033
COMMON-MODE RANGE (V)
2.5 2.0 1.5 1.0 0.5 0
0
0.5
1.0
1.5 VREF (V)
2.0
2.5
3.0
Figure 28. Input Common-Mode Range vs. VREF (0 to VREF Range, VDD = 5 V)
4.5 4.0
COMMON-MODE RANGE (V)
3.5 3.0 2.5 2.0 1.5 1.0
03713-0-034
V+
27
V-
220 220
3.75V 2.5V 1.25V VIN+
0.5 0 0.1 0.6 1.1 VREF (V) 1.6 2.1
AD7933/ AD7934
3.75V 2.5V 1.25V VIN- VREF
V+
27
2.6
A
V-
10k
Driving Differential Inputs
Differential operation requires that VIN+ and VIN- be simultaneously driven with two equal signals that are 180 out of phase. The common mode must be set up externally and have a range that is determined by VREF, the power supply, and the particular amplifier used to drive the analog inputs. Differential modes of operation with either an ac or dc input provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform singleended-to-differential conversion.
Figure 30. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal
220 2 x VREF p-p GND 390
V+
27
V-
220 220 220
3.75V 2.5V 1.25V VIN+
AD7933/ AD7934
3.75V 2.5V 1.25V VIN- VREF
V+
27
A
V-
10k
0.47F
03713-0-036
20k
Figure 31. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a Differential Signal
Rev. PrG | Page 21 of 32
03713-0-035
Figure 29. Input Common-Mode Range vs. VREF (2 x VREF Range, VDD = 5 V)
0.47F
20k
AD7933/AD7934
Pseudo-Differential Mode
The AD7933/AD7934 can have two pseudo-differential pairs by setting Bits MODE0 and MODE1 in the control register to 1, 0, respectively. VIN+ is connected to the signal source that must have an amplitude of VREF to make use of the full dynamic range of the part. ADC input is applied to the VIN- pin. The voltage applied to this input provides an offset from ground or a pseudo ground for the VIN+ input. The benefit of pseudo-differential inputs is that they separate the analog input signal ground from the ADC's ground allowing dc common-mode voltages to be cancelled. Figure 32 shows a connection diagram for the pseudo-differential mode.
VREF p-p VIN+
Preliminary Technical Data
POWER ON WRITE TO THE CONTROL REGISTER TO SET UP OPERATING MODE, ANALOG INPUT AND OUTPUT CONFIGURATION SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED CHANNEL TO CONVERT ON (ADD1 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION ON THE SELECTED CHANNEL. INITIATE A READ CYCLE TO READ THE DATA FROM THE SELECTED CHANNEL.
Figure 33. Normal Multichannel Operation Flow Chart
Using the Sequencer: Consecutive Sequence (SEQ0 = 1, SEQ1 = 1)
A sequence of consecutive channels can be converted beginning with Channel 0 and ending with a final channel selected by writing to Bits ADD1 and ADD0 in the control register. This is done by setting the SEQ0 and SEQ1 bits in the control register both to 1. Once the control register is written to set this mode up, the next conversion is on Channel 0, then Channel 1, and so on until the channel selected by the address bits, ADD1 and ADD0, is reached. The ADC then returns to Channel 0 and starts the sequence again. The WR input must be kept high to ensure that the control register is not accidentally overwritten and the sequence interrupted. This pattern continues until such time as the AD7933/AD7934 is written to. Figure 34 shows the flow chart of the consecutive sequence mode.
POWER ON WRITE TO THE CONTROL REGISTER TO SET UP OPERATING MODE, ANALOG INPUT AND OUTPUT CONFIGURATION SELECT FINAL CHANNEL (ADD1 AND ADD0) IN CONSECUTIVE SEQUENCE. SET SEQ0 = 1 SEQ1 = 1.
AD7933/ AD7934*
VIN- DC INPUT VOLTAGE RANGE 100mV VREF 0.47F
03713-0-037
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 32. Pseudo-Differential Mode Connection Diagram
ANALOG INPUT SELECTION
As shown in Table 9, users can set up their analog input configuration by setting the values in Bits MODE0 and MODE1 in the control register. Assuming the configuration is chosen, there are two different ways of selecting the analog input to be converted depending on the state of the SEQ0 and SEQ1 bits in the control register.
Normal Multichannel Operation (SEQ0 = SEQ1 = 0)
Any one of four analog input channels or two pairs of channels may be selected for conversion in any order by setting the SEQ0 and SEQ1 bits in the control register both to 0. The channel to be converted is selected by writing to Bits ADD1 and ADD0 in the control register to program the multiplexer prior to the conversion. This mode of operation is of a normal multichannel ADC where each data write selects the next channel for conversion. Figure 33 shows a flow chart of this mode of operation. The channel configurations are shown in Table 9.
Figure 34. Consecutive Sequence Mode Flow Chart
REFERENCE SECTION
The AD7933/AD7934 can operate with either the on-chip reference or an external reference. The internal reference is selected by setting the REF bit in the internal control register to 1. A block diagram of the internal reference circuitry is shown in Figure 35. The internal reference circuitry includes an on-chip 2.5 V band gap reference and a reference buffer. When using the internal reference, the VREFIN/VREFOUT pin should be decoupled to AGND with a 0.47 F capacitor. This internal reference not only provides the reference for the analog-to-digital conversion, but it also is used externally in the system. It is recommended that the reference output is buffered using an external precision op amp before applying it anywhere in the system.
Rev. PrG | Page 22 of 32
03713-0-039
CONTINUOUSLY CONVERT ON A CONSECUTIVE SEQUENCE OF CHANNELS FROM CHANNEL 0 UP TO AND INCLUDING THE PREVIOUSLY SELECTED FINAL CHANNEL ON ADD1 AND ADD0 WITH EACH CONVST PULSE.
03713-0-038
INITIATE A WRITE CYCLE TO SELECT THE NEXT CHANNEL TO BE CONVERTED ON BY CHANGING THE VALUES OF BITS ADD2 TO ADD0 IN THE CONTROL REGISTER. SEQ0 = SEQ1 = 0.
Preliminary Technical Data
BUFFER VREFIN/ VREFOUT REFERENCE
AD7933/AD7934
Example 2
VIN MAX = VDD + 0.3
ADC
AD7933/ AD7934
03713-0-040
VIN MAX = VREF + VREF/2 If VDD = 3.6 V, then VIN MAX = 3.9 V. Therefore, 3 x VREF/2 = 3.6 V. VREF MAX = 2.6 V Therefore, when operating with at VDD = 3 V, the value of VREF can range from 100 mV to a maximum value of 2.4 V. When VDD = 2.7 V, VREF MAX = 2 V. These examples show that the maximum reference applied to the AD7933/AD7934 is directly dependant on the value applied to VDD. The performance of the part at different reference values is shown in Figures TBD to TBD. The value of the reference sets the analog input span and the common-mode voltage range. Errors in the reference source result in gain errors in the AD7933/AD7934 transfer function and add to the specified full-scale errors on the part. Table 11 lists suitable voltage references available from ADI that could be used, and Figure 36 shows a typical connection diagram for an external reference.
Table 11. Examples of Suitable Voltage References
Output Voltage 2.5/3 2.5 2.048 Initial Accuracy (% max) 0.04 0.04 0.05 Operating Current (A) 1000 500 500
AD7933/ AD7934*
NC NC 2.5V NC 0.1F VREF
7 6
Figure 35. Internal Reference Circuit Block Diagram
Alternatively, an external reference can be applied to the VREFIN/VREFOUT pin of the AD7933/AD7934. An external reference input is selected by setting the REF bit in the internal control register to 0. When using an external reference, the VREFIN/VREFOUT pin should be decoupled to AGND with a 0.1 F capacitor. When operating in differential mode, the external reference input range is 0.1 V to 3.5V, and in single-ended and pseudo-differential mode, the external reference input range is 0.1 V to VDD. In all cases, the specified reference is 2.5 V. It is important to ensure that, when choosing the reference value, the maximum analog input range (VIN MAX) is never greater than VDD + 0.3 V to comply with the maximum ratings of the device. In pseudo differential mode, the user must ensure that VREFIN - VIN- VDD. The following two examples calculate the maximum VREF input that can be used when operating the AD7933/AD7934 in differential mode with a VDD of 5 V and 3 V, respectively.
Example 1
VIN MAX = VDD + 0.3 VIN MAX = VREF + VREF/2 If VDD = 5 V, then VIN MAX = 5.3 V. Therefore, 3 x VREF/2 = 5.3 V. VREF MAX = 3.5 V
Reference AD780 ADR421 ADR420
AD780
NC VDD
1
O/PSELECT 8
2 +VIN 3 TEMP VOUT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. Typical VREF Connection Program
Rev. PrG | Page 23 of 32
03713-0-041
Therefore, when operating at VDD = 5 V, the value of VREF can range from 100 mV to a maximum value of 3.5 V. When VDD = 4.75 V, VREF MAX = 3.17 V.
0.1F
10nF
0.1F
4 GND
TRIM 5
NC = NO CONNECT
AD7933/AD7934
Digital Inputs
The digital inputs applied to the AD7933/AD7934 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the AVDD + 0.3 V limit that is on the analog inputs. Another advantage of the digital inputs not being restricted by the AVDD + 0.3 V limit is the fact that power supply sequencing issues are avoided. If any of these inputs are applied before AVDD, then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to AVDD.
Preliminary Technical Data
PARALLEL INTERFACE
The AD7933/AD7934 have a flexible, high speed, parallel interface. This interface is 12-bits (AD7934) or 10-bits (AD7933) wide and is capable of operating in either word (W/B tied high) or byte (W/B tied low) mode. The CONVST signal is used to initiate conversions, and when operating in auto shutdown or auto standby mode, it is used to power up the ADC. A falling edge on the CONVST signal is used to initiate conversions, and it also puts the ADC track-and-hold into track. Once the CONVST signal goes low, the BUSY signal goes high for the duration of the conversion. In between conversions, CONVST must be brought high for a minimum time of t1. This must happen after the 14th rising edge of CLKIN; otherwise, the conversion will be aborted and the track-and-hold will go back into track. At the end of the conversion, BUSY goes low and can be used to activate an interrupt service routine. The CS and RD lines are then activated in parallel to read the 12 bits or 10 bits of conversion data. When power supplies are first applied to the device, a rising edge on CONVST puts the track-and-hold into track. The acquisition time of 135 ns minimum must be allowed before CONVST is brought low to initiate a conversion. The ADC will then go into hold on the falling edge of CONVST and back into track on the 13th rising edge of CLKIN after this (see Figure 37). When operating the device in auto shutdown or auto standby mode, where the ADC powers down at the end of each conversion, a rising edge on the CONVST signal is used to power up the device.
B A
VDRIVE Input
The AD7933/AD7934 has a VDRIVE feature. VDRIVE controls the voltage at which the parallel interface operates. VDRIVE allows the ADC to easily interface to 1.8 V, 3 V, and 5 V processors. VDRIVE of 1.8 V can only be used if VDD = 2.7 V to 3.6 V. For example, if the AD7933/AD7934 operated with an AVDD of 5 V and the VDRIVE pin could be powered from a 3 V supply, the AD7933/AD7934 has better dynamic performance with an AVDD of 5 V while still being able to interface to 3 V processors. Care should be taken to ensure VDRIVE does not exceed AVDD by more than 0.3 V (see Table 4).
t1
CONVST 1 CLKIN 2 3 4
tCONVERT
5
12
13
14
t2 t20 t3
BUSY
t9 tAQUISITION
INTERNAL TRACK/HOLD
CS
RD
t10 t13
t12
t11 t14
DB0 TO DB11
THREE-STATE
DATA
THREE-STATE
tQUIET
DB0 TO DB11
OLD DATA
DATA
Figure 37. AD7933/AD7934 Parallel Interface--Conversion and Read Cycle in Word Mode (W/B = 1)
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03713-0-004
WITH CS AND RD TIED LOW
AD7933/AD7934
Reading Data from the AD7933/AD7934
With the W/B pin tied logic high, the AD7933/AD7934 interface operates in word mode. In this case, a single read operation from the device accesses the conversion data-word on Pins DB0/DB2 to DB11. The DB8/HBEN pin assumes its DB8 function. With the W/B pin tied to logic low, the AD7933/AD7934 interface operates in byte mode. In this case, the DB8/HBEN pin assumes its HBEN function. Conversion data from the AD7933/ AD7934 must be accessed in two read operations with 8 bits of data provided on DB0 to DB7 for each of the read operations. The HBEN pin determines whether the read operation accesses the high byte or the low byte of the12or 10-bit word. For a low byte read, DB0 to DB7 provide the eight LSBs of the 12-bit word. For 10-bit operation, the two LSBs of the low byte are 0s and are followed by 6 bits of conversion data. For a high byte read, DB0 to DB3 provide the 4 MSBs of the 12-/10-bit word. DB4 of the high byte is always 0 and DB5 and DB6 of the high byte provide the Channel ID. Figure 37 shows the read cycle timing diagram for a 12-/10-bit
Preliminary Technical Data
transfer. When operated in word mode, the HBEN input does not exist and only the first read operation is required to access data from the device. When operated in byte mode, the two read cycles shown in Figure 38 are required to access the full dataword from the device. The CS and RD signals are gated internally and level triggered active low. In either word mode or byte mode, CS and RD may be tied together as the timing specification t10 and t11 is 0 ns minimum. The data is placed onto the data bus a time t13 after both CS and RD go low. The RD rising edge can be used to latch data out of the device. After a time, t14, the data lines will become three-stated. Alternatively, CS and RD can be tied permanently low and the conversion data will be valid and placed onto the data bus a time, t9, before the falling edge of BUSY.
HBEN/DB8
t15
CS
t16
t15
t16
t10
RD
t11 t12
t17 t14
DB0 TO DB7
LOW BYTE
HIGH BYTE
Figure 38. AD7933/AD7934 Parallel Interface--Read Cycle Timing for Byte Mode Operation (W/B = 0)
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03713-0-005
t13
AD7933/AD7934
Writing Data to the AD7933/AD7934
With W/B tied logic high, a single write operation transfers the full data-word on DB0 to DB11 to the control register on the AD7933/AD7934. The DB8/HBEN pin assumes its DB8 function. Data written to the AD7933/AD7934 should be provided on the DB0 to DB11 inputs with DB0 being the LSB of the data-word. With W/B tied logic low, the AD7933/AD7934 requires two write operations to transfer a full 12-bit word. DB8/HBEN assumes its HBEN function. Data written to the AD7933/AD7934 should be provided on the DB0 to DB7 inputs. HBEN determines whether the byte written is high byte or low byte data. The low byte of the data-word has DB0 being the LSB of the full data-word. For the high byte write, HBEN should be high and the data on the DB0 input should be data bit 8 of the 12 bit word. Figure 39 shows the write cycle timing diagram of the AD7933/AD7934. When operated in word mode, the HBEN input does not exist and only the one write operation is required
Preliminary Technical Data
to write the word of data to the device. Data should be provided on DB0 to DB11. When operated in byte mode, the two write cycles shown in Figure 40 are required to write the full dataword to the AD7933/AD7934. In Figure 40, the first write transfers the lower 8 bits of the data-word from DB0 to DB7 and the second write transfers the upper 4 bits of the data-word. When writing to the AD7933/AD7934, the top 4 bits in the high byte must be 0s. The data is latched into the device on the rising edge of WR. The data needs to be setup a time, t7, before the WR rising edge and held for a time, t8, after the WR rising edge. The CS and WR signals are gated internally. CS and WR may be tied together as the timing specification for t4 and t5 is 0 ns minimum (assuming CS and RD have not already been tied together).
CS
WR
t4
t6 t7 t8
t5
03713-0-002
DB0 TO DB11
DATA
Figure 39. AD7933/AD7934 Parallel Interface--Write Cycle Timing for Word Mode Operation (W/B = 1)
HBEN/DB8
t18
CS
t19
t18
t19
t4
WR
t5 t6 t7 t8
t17
DB0 TO DB7
LOW BYTE
HIGH BYTE
Figure 40. AD7933/AD7934 Parallel Interface--Write Cycle Timing for Byte Mode Operation (W/B = 0)
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03713-0-003
Preliminary Technical Data
POWER MODES OF OPERATION
The AD7933/AD7934 have four different power modes of operation. These modes are designed to provide flexible power management options. Different options can be chosen to optimize the power dissipation/throughput rate ratio for differing applications. The mode of operation is selected by the power management bits, PM1 and PM0, in the control register, as detailed in Table 8. When power is first applied to the AD7933/AD7934 an on-chip, power-on reset circuit ensures the default power-up condition is normal mode. Note that, after power-on, track-and-hold is in hold mode and the first rising edge of CONVST places the track-and-hold into track mode.
AD7933/AD7934
internal reference, the power-up time is typically TBD, and with an external reference, the power-up time is typically TBD. The user should ensure that the power-up time has elapsed before initiating a conversion.
Auto Standby (PM1 = 1; PM0 = 0)
In this mode of operation, the AD7933/AD7934 automatically enter standby mode at the end of each conversion. When this mode is entered, all circuitry on the AD7933/AD7934 is powered down except for the reference and reference buffer. Also, track-and-hold goes into hold at this point and remains in hold as long as the device is in standby The part remains in standby until the next rising edge of CONVST powers up the device, which takes at least TBD. The user should ensure this power-up time has elapsed before initiating another conversion, as shown in Figure 41. This rising edge of CONVST also places track-and-hold back into track mode.
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate performance because the user does not have to worry about any power-up times because the AD7933/AD7934 remain fully powered up at all times. At power-on reset, this mode is the default setting in the control register.
Full Shutdown Mode (PM1 = 1; PM0 = 1)
When this mode is entered, all circuitry on the AD7933/AD7934 is powered down upon completion of the write operation, i.e., on rising edge of WR. The part retains the information in the control register while the part is in shutdown. The AD7933/AD7934 remain in full shutdown mode, and track-and-hold in hold mode, until the power management bits (PM1 and PM0) in the control register are changed. If a write to the control register occurs while the part is in full shutdown mode, and the power management bits are changed to PM0 = PM1 = 0, i.e., normal mode, the part begins to power up on the WR rising edge and the track and hold returns to track.. To ensure the part is fully powered up before a conversion is initiated, the power-up time, TBD, should be allowed before the CONVST falling edge; otherwise, invalid data is read.
Auto Shutdown (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7933/AD7934 automatically enter full shutdown at the end of each conversion, which is shown at Point A in Figure 37. In shutdown mode, all internal circuitry on the device is powered. The part retains information in the control register during shutdown. It remains in shutdown mode until the next rising edge of CONVST (see Point B in Figure 37). In order to keep the device in shutdown for as long as possible, CONVST should idle low between conversions as shown in Figure 41. On this rising edge, the part begins to power-up and track-and-hold returns to track mode. The power-up time required depends on whether the user is operating with the internal or external reference. With the
tPOWER-UP
A B
CONVST 1 CLKIN
03713-0-048
14
1
14
BUSY
Figure 41. Auto-Shutdown/Auto-Standby Mode
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AD7933/AD7934
POWER VS. THROUGHPUT RATE
A big advantage of powering the ADC down after a conversion is that the power consumption of the part is significantly reduced at lower throughput rates. When using the different power modes, the AD7933/AD7934 is only powered up for the duration of the conversion. Therefore, the average power consumption per cycle is significantly reduced. Figure 42 and Figure 43 show plots of the power versus the throughput when operating in auto shutdown and auto standby modes.
A0 TO A15
Preliminary Technical Data
OPTIONAL ADDRESS BUS CONVST
ADSP-21xx*
DMS IRQ2 WR RD ADDRESS DECODER CS
AD7933/ AD7934*
BUSY WR RD DB0 TO DB11
D0 TO D23
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 44. Interfacing to the ADSP-21xx
AD7933/AD7934 to ADSP-21065L Interface
Figure 45 shows a typical interface between the AD7933/AD7934 and the ADSP-21065L SHARC processor. This interface is an example of one of three DMA handshake modes. The MSx control line is actually three memory select lines. Internal ADDR25-24 are decoded into MS3-0, these lines are then asserted as chip selects. The DMAR1 (DMA request 1) is used in this setup as the interrupt to signal the end of the conversion. The rest of the interface is standard handshaking operation.
OPTIONAL
Figure 42. Power vs. Throughput in Auto Shutdown Mode
ADDR0 TO ADDR23
ADDRESS BUS
CONVST
MSX
ADDRESS LATCH ADDRESS BUS
AD7933/ AD7934*
CS BUSY RD WR DB0 TO DB11
ADSP-21065L*
DMAR1 RD WR
ADDRESS DECODER
D0 TO D31
DATA BUS
MICROPROCESSOR INTERFACING
AD7933/AD7934 to ADSP-21xx Interface
Figure 44 shows the AD7933/AD7934 interfaced to the ADSP21xx series of DSPs as a memory mapped device. A single wait state may be necessary to interface the AD7933/AD7934 to the ADSP-21xx, depending on the clock speed of the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx family User's Manual for details). The following instruction reads from the AD7933/AD7934: MR = DM (ADC) where ADC is the address of the AD7933/AD7934.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 45. Interfacing to the ADSP-21065L
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03713-0-045
Figure 43. Power vs. Throughput in Auto Standby Mode
03713-0-044
Preliminary Technical Data
AD7933/AD7934 to TMS32020, TMS320C25, and TMS320C5x Interface
Parallel interfaces between the AD7933/AD7934 and the TMS32020, TMS320C25 and TMS320C5x family of DSPs are shown in Figure 46. The memory mapped address chosen for the AD7933/AD7934 should be chosen to fall in the I/O memory space of the DSPs. The parallel interface on the AD7933/AD7934 is fast enough to interface to the TMS32020 with no extra wait states. If high speed glue logic, such as 74AS devices, are used to drive the RD and the WR lines when interfacing to the TMS320C25, then again, no wait states are necessary. However, if slower logic is used, data accesses may be slowed sufficiently when reading from and writing to the part to require the insertion of one wait state. Extra wait states will be necessary when using the TMS320C5x at their fastest clock speeds (see the TMS320C5x User's Guide for details). Data is read from the ADC using the following instruction: IN D, ADC where D is the data memory address, and ADC is the AD7933/AD7934 address.
OPTIONAL
RD
AD7933/AD7934
AD7933/AD7934 to 80C186 Interface
Figure 47 shows the AD7933/AD7934 interfaced to the 80C186 microprocessor. The 80C186 DMA controller provides two independent high speed DMA channels where data transfer can occur between memory and I/O spaces. Each data transfer consumes two bus cycles, one cycle to fetch data and the other to store data. After the AD7933/AD7934 has finished a conversion, the BUSY line generates a DMA request to Channel 1 (DRQ1). As a result of the interrupt, the processor performs a DMA READ operation which also resets the interrupt latch. Sufficient priority must be assigned to the DMA channel to ensure that the DMA request will be serviced before the completion of the next conversion.
OPTIONAL
AD0 TO AD15 A16 TO A19 ALE
ADDRESS/DATA BUS
CONVST
ADDRESS LATCH ADDRESS BUS
AD7933/ AD7934*
CS
80C186*
ADDRESS DECODER Q R S
DRQ1
BUSY RD WR DATA BUS DB0 TO DB11
03713-0-047
A0 TO A15
ADDRESS BUS
CONVST
WR
TMS32020/ TMS320C25/ TMS320C50*
IS READY MSC STRB R/W
AD7933/ AD7934*
ADDRESS EN DECODER CS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. Interfacing to the 80C186
TMS320C25 ONLY WR RD INTX DMD0 TO DMD15 DATA BUS BUSY DB11 TO DB0
03713-0-046
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. Interfacing to the TMS32020/C25/C5x
Rev. PrG | Page 29 of 32
AD7933/AD7934 APPLICATION HINTS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7933/AD7934 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the ground pins on the AD7933/AD7934 as possible. Avoid running digital lines under the device as this couples noise onto the die. The analog ground plane should be allowed to run under the AD7933/AD7934 to avoid noise coupling. The power supply lines to the AD7933/AD7934 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated
Preliminary Technical Data
to ground planes, while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 F tantalum capacitors in parallel with 0.1 F capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device.
EVALUATING THE AD7933/AD7934 PERFORMANCE
The recommended layout for the AD7933/AD7934 is outlined in the evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7933/AD7934 evaluation board, as well as many other ADI evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7933/AD7934. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7933/AD7934. The software and documentation are on the CD that ships with the evaluation board.
Rev. PrG | Page 30 of 32
Preliminary Technical Data OUTLINE DIMENSIONS
9.80 9.70 9.60
AD7933/AD7934
28
15
4.50 4.40 4.30
1 14
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 48. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7934BRU AD7933BRU EVAL-AD7934CB2 EVAL-AD7933CB3 EVAL-CONTROL BRD24 Temperature Range -40C to +85C -40C to +85C Linearity Error (LSB)1 1 1 Package Option RU-28 RU-28 Package Descriptions Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Evaluation Board Evaluation Board Controller Board
1 2 3
Linearity error here refers to integral linearity error. This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes. This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes. 4 Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (EVAL-AD7934CB), the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the EVAL-AD7933/34CB evaluation board technical note for more details.
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AD7933/AD7934 NOTES
Preliminary Technical Data
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR03713-0-8/04(PrG)
Rev. PrG | Page 32 of 32

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